1. Technical Field
This application relates generally to electronic analog-to-digital converters.
2. Description of the Prior Art
In the majority of known electronic analog-to-digital converters the consecutive conversion of the analog input voltage into the digital output representation thereof is performed. Such a 5-bit converter is described in the published patent application DE 24 14 865 A1. When determining the value of a specific bit, across a gated amplifier, i.e. one of the 5 present, which is picked out by a logic unit, the voltage of the level assigned to this bit is fed to either input of a comparator, to the other input of which the analog voltage to be converted is fed. The bit values are determined by the logic unit. The determination process starts at the most significant bit and is continued step-by-step to the bit with the smallest weight.
Further, from the published patent application DE 38 29 730 A1 there has been known a sequential electronic analog-to-digital converter, in which the analog voltage input and the output of a digital-to-analog converter are connected to the inverting input of a comparator, the other input of which is grounded and the output of which is connected to the input of a register. The output of the register is connected by bus to the input of the afore-mentioned digital-analog converter. The described converter performs a fast convergence to the actual digital representation of the input voltage.
In sequential electronic analog-to-digital converters some time is needed to perform the quantization of the input voltage into all bits of the output digital representation. Therefore a conversion of fast varying signals is not feasible. Additionally, because of the non-synchronous appearance of digital output signals, latches are needed, which increases the complexity of such converters.
In parallel electronic analog-to-digital converters, however, for the complete conversion only one step is needed and hence the quantization time is shorter. There has been known a flash analog-to-digital converter. In the N-bit flash converter the input voltage is fed to either inputs of 2.sup.N -1 comparators, the other inputs of which are connected to the outputs of a voltage divider being composed of the same number of resistors to obtain the 2.sup.N -1 quantization voltage levels. The output of each comparator is through its own latch-all latches being connected to a common clock-connected to the relevant input of an encoder, at the output of which the digital representation of the input voltage appears. At high N the circuitry of the flash converter is of a considerable size and therefore the upper frequency operating limit is set by the time of flight of a signal across the converter.